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? semiconductor components industries, llc, 2013 september, 2013 ? rev. 4 1 publication order number: TLV271/d TLV271 single-channel, rail-to-rail output, 3 mhz bw operational amplifier the TLV271 operational amplifier provides rail ? to ? rail output operation. the output can swing within 320 mv to the positive rail and 50 mv to the negative rail. this rail ? to ? rail operation enables the user to make optimal use of the entire supply voltage range while taking advantage of 3 mhz bandwidth. the TLV271 can operate on supply voltage as low as 2.7 v over the temperature range of ? 40 c to 105 c. the high bandwidth provides a slew rate of 2.4 v/ s while only consuming 550 a of quiescent current. likewise the TLV271 can run on a supply voltage as high as 16 v making it ideal for a broad range of battery ? operated applications. since this is a cmos device it has high input impedance and low bias currents making it ideal for interfacing to a wide variety of signal sensors. in addition it comes in a small tsop ? 5 package with two pinout styles allowing for use in high ? density pcb?s. features ? rail ? to ? rail output ? wide bandwidth: 3 mhz ? high slew rate: 2.4 v/ s ? wide power ? supply range: 2.7 v to 16 v ? low supply current: 550 a ? low input bias current: 45 pa ? wide temperature range: ? 40 c to 105 c ? small package: 5 pin tsop ? 5 (same as sot23 ? 5) ? these devices are pb ? free, halogen free/bfr free and are rohs compliant applications ? notebook computers ? portable instruments 1 5 xxxayw tsop ? 5 (sot23 ? 5) sn suffix case 483 marking diagram device package shipping ? ordering information 1 5 2 3 4 in+ out v dd v ee in ? style 1 pinout (sn1t1) (top view) + ? pin connections http://onsemi.com TLV271sn1t1g (style 1 pinout) tsop ? 5 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. xxx = adg (TLV271sn1t1g) = adh (TLV271sn2t1g) a = assembly location y = year w = work week = pb ? free package (note: microdot may be in either location) 1 5 1 5 2 3 4 in+ out v ee v dd in ? style 2 pinout (sn2t1) (top view) + ? TLV271sn2t1g (style 2 pinout) tsop ? 5 (pb ? free) 3000 / tape & reel
TLV271 http://onsemi.com 2 maximum ratings symbol rating value unit v dd supply voltage (note 1) 16.5 v v id input differential voltage (note 2) supply voltage v v i input common mode voltage range (note 1) ? 0.2 v to (v dd + 0.2 v) v i i maximum input current 10 ma i o output current range 100 ma continuous total power dissipation (note 1) 200 mw t j maximum junction temperature 150 c ja thermal resistance 333 c/w t stg operating temperature range (free ? air) ? 40 to 105 c t stg storage temperature ? 65 to 150 c mounting temperature (infrared or convection ? 20 sec) 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. continuous short ? circuit operation to ground at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150 c. output currents in excess of 45 ma over long term may adversely affect reliability. shorting output to either v+ or v ? will adversely affect reliability. 2. esd data available upon request. dc electrical characteristics (v dd = 2.7v, 3.3v, 5v & 5 v (note 3), t a = 25 c, r l 10 k unless otherwise noted) parameter symbol conditions min typ max unit input offset voltage v io vic = v dd /2, v o = v dd /2, r l = 10 k , r s = 50 0.5 5 mv t a = ? 40 c to +105 c 7 offset voltage drift icv os vic = v dd /2, v o = v dd /2, r l = 10 k , r s = 50 2 v/ c common mode rejection ratio cmrr 0 v vic v dd ? 1.35 v, r s = 50 v dd = 2.7 v 58 70 db t a = ? 40 c to +105 c 55 0 v vic v dd ? 1.35 v, r s = 50 v dd = 5 v 65 130 t a = ? 40 c to +105 c 62 0 v vic v dd ? 1.35 v, r s = 50 v dd = 5 v 69 140 t a = ? 40 c to +105 c 66 power supply rejection ratio psrr v dd = 2.7 v to 16 v, vic = v dd /2, no load 70 135 db t a = ? 40 c to +105 c 65 large signal voltage gain a vd v o(pp) = v dd /2, r l = 10 k v dd = 2.7 v 97 106 db t a = ? 40 c to +105 c 76 v o(pp) = v dd /2, r l = 10 k v dd = 3.3 v 97 123 t a = ? 40 c to +105 c 76 v o(pp) = v dd /2, r l = 10 k v dd = 5 v 100 127 t a = ? 40 c to +105 c 86 v o(pp) = v dd /2, r l = 10 k v dd = 5 v 100 130 t a = ? 40 c to +105 c 90 input bias current i b v dd = 5 v, vic = v dd /2, v o = v dd /2, r s = 50 t a = 25 c 45 150 pa t a = 105 c 1000 3. v dd = 5 v is shorthand for v dd = +5 v and v ee = ? 5 v.
TLV271 http://onsemi.com 3 dc electrical characteristics (v dd = 2.7v, 3.3v, 5v & 5 v (note 3), t a = 25 c, r l 10 k unless otherwise noted) parameter unit max typ min conditions symbol input offset current i io v dd = 5 v, vic = v dd /2, v o = v dd /2, r s = 50 t a = 25 c 45 150 pa t a = 105 c 1000 differential input resistance r i(d) 1000 g common ? mode input capacitance c ic f = 21 khz 8 pf output swing (high ? level) v oh vic = v dd /2, i oh = ? 1 ma v dd = 2.7 v 2.55 2.58 v t a = ? 40 c to +105 c 2.48 vic = v dd /2, i oh = ? 1 ma v dd = 3.3 v 3.15 3.21 t a = ? 40 c to +105 c 3.00 vic = v dd /2, i oh = ? 1 ma v dd = 5 v 4.8 4.93 t a = ? 40 c to +105 c 4.75 vic = v dd /2, i oh = ? 1 ma v dd = 5 v 4.92 4.96 t a = ? 40 c to +105 c 4.9 vic = v dd /2, i oh = ? 5 ma v dd = 2.7 v 1.9 2.1 v t a = ? 40 c to +105 c 1.5 vic = v dd /2, i oh = ? 5 ma v dd = 3.3 v 2.5 2.89 t a = ? 40 c to +105 c 2.1 vic = v dd /2, i oh = ? 5 ma v dd = 5 v 4.5 4.68 t a = ? 40 c to +105 c 4.35 vic = v dd /2, i oh = ? 5 ma v dd = 5 v 4.7 4.78 t a = ? 40 c to +105 c 4.65 output swing (low ? level) v ol vic = v dd /2, i ol = ? 1 ma v dd = 2.7 v 0.1 0.15 v t a = ? 40 c to +105 c 0.22 vic = v dd /2, i ol = ? 1 ma v dd = 3.3 v 0.03 0.15 t a = ? 40 c to +105 c 0.22 vic = v dd /2, i ol = ? 1 ma v dd = 5 v 0.03 0.1 t a = ? 40 c to +105 c 0.15 vic = v dd /2, i ol = ? 1 ma v dd = 5 v 0.05 0.08 t a = ? 40 c to +105 c 0.1 vic = v dd /2, i ol = ? 5 ma v dd = 2.7 v 0.5 0.7 v t a = ? 40 c to +105 c 1.1 vic = v dd /2, i ol = ? 5 ma v dd = 3.3 v 0.13 0.7 t a = ? 40 c to +105 c 1.1 vic = v dd /2, i ol = ? 5 ma v dd = 5 v 0.13 0.4 t a = ? 40 c to +105 c 0.5 vic = v dd /2, i ol = ? 5 ma v dd = 5 v 0.16 0.3 t a = ? 40 c to +105 c 0.35 3. v dd = 5 v is shorthand for v dd = +5 v and v ee = ? 5 v.
TLV271 http://onsemi.com 4 dc electrical characteristics (v dd = 2.7v, 3.3v, 5v & 5 v (note 3), t a = 25 c, r l 10 k unless otherwise noted) parameter unit max typ min conditions symbol output current i o v o = 0.5 v from rail, v dd = 2.7 v positive rail 4.0 ma negative rail 5.0 v o = 0.5 v from rail, v dd = 5 v positive rail 7.0 negative rail 8.0 v o = 0.5 v from rail, v dd = 10 v positive rail 13 negative rail 12 power supply quiescent current i dd v o = v dd /2 v dd = 2.7 v 380 560 a v dd = 3.3 v 385 620 v dd = 5 v 390 660 v dd = 10 v 400 800 t a = ? 40 c to +105 c 1000 3. v dd = 5 v is shorthand for v dd = +5 v and v ee = ? 5 v. ac electrical characteristics (v dd = 2.7 v, 5 v, & 5 v (note 4), t a = 25 c, and r l 10 k unless otherwise noted) parameter symbol conditions min typ max unit unity gain bandwidth ugbw r l = 2 k , c l = 10 pf v dd = 2.7 v 3.2 mhz v dd = 5 v to 10 v 3.5 slew rate at unity gain sr v o(pp) = v dd /2, r l = 10 k , c l = 50 pf v dd = 2.7 v 1.35 2.1 v/ s t a = ? 40 c to +105 c 1 v o(pp) = v dd /2, r l = 10 k , c l = 50 pf v dd = 5 v 1.45 2.3 t a = ? 40 c to +105 c 1.2 v o(pp) = v dd /2, r l = 10 k , c l = 50 pf v dd = 5 v 1.8 2.6 t a = ? 40 c to +105 c 1.3 phase margin m r l = 2 k , c l = 10 pf 45 gain margin r l = 2 k , c l = 10 pf 14 db settling time to 0.1% t s v ? step(pp) = 1 v, av = ? 1, r l = 2 k , c l = 10 pf v dd = 2.7 v 2.9 s v ? step(pp) = 1 v, av = ? 1, r l = 2 k , c l = 47 pf v dd = 5 v, 5 v 2.0 total harmonic distortion plus noise thd+n v dd = 2.7 v, v o(pp) = v dd /2, r l = 2 k , f = 10 khz av = 1 0.004 % av = 10 0.04 av = 100 0.3 v dd = 5 v, 5 v, v o(pp) = v dd /2, r l = 2 k , f = 10 khz av = 1 0.004 av = 10 0.04 av = 100 0.03 input ? referred voltage noise e n f = 1 khz 30 nv/ hz f = 10 khz 20 input ? referred current noise i n f = 1 khz 0.6 fa/ hz 4. v dd = 5 v is shorthand for v dd = +5 v and v ee = ? 5 v.
TLV271 http://onsemi.com 5 frequency (hz) cmrr (db) figure 1. cmrr vs. frequency 2.7 v 10 v 5 v r l = 2 k 25 c 250 200 150 100 50 0 ? 50 ? 100 ? 40 ? 25 ? 10 5 20 35 50 65 80 95 110 125 figure 2. input bias and offset current vs. temperature free air temperature ( c) input bias and offset current (pa) input bias input offset 2.5 0 low level output current (ma) low level output voltage (v) figure 3. 2.5 v v ol vs. i out 10 20 30 40 50 60 70 80 ? 40 c 25 c 105 c v dd = 2.5 v 0 1020 30 4050 607080 low level output current (ma) figure 4. 2.5 v v oh vs. i out high level output voltage (v) 2.5 v dd = 2.5 v ? 40 c 25 c 105 c 3.3 0 low level output current (ma) low level output voltage (v) figure 5. 3.3 v v ol vs. i out 10 20 30 40 50 60 70 80 90 ? 40 c 25 c 105 c v dd = 3.3 v 3.3 010 203040 50607080 90 high level output voltage (v) high level output current (ma) figure 6. 3.3 v v oh vs. i out 25 c ? 40 c 105 c v dd = 3.3 v 2.5 v 0 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 10 100 1k 10k 100k 1m 2 1.5 1 0.5 0 2 1.5 1 0.5 0 3 2.7 2.4 2.1 1.8 1.5 1.2 0.9 0.6 0.3 0 3 2.7 2.4 2.1 1.8 1.5 1.2 0.9 0.6 0.3 0
TLV271 http://onsemi.com 6 5 010 203040 50607080 low level output voltage (v) low level output current (ma) figure 7. v ol vs. i out 25 c ? 40 c 105 c v dd = 5.0 v 4 3 2 1 0 5 010 203040 50607080 4 3 2 1 0 high level output voltage (v) high level output current (ma) figure 8. v oh vs. i out v dd = 5.0 v 25 c ? 40 c 105 c 10 010 203040 50607080 low level output voltage (v) low level output current (ma) figure 9. 10 v v ol vs. i out v dd = 10 v 25 c 105 c ? 40 c 10 01020304050607080 high level output voltage (v) high level output current (ma) figure 10. 10 v v oh vs. i out v dd = 10 v 25 c 105 c ? 40 c 12 0.01 0.1 1 10 100 1k 10k frequency (khz) figure 11. peak ? to ? peak output vs. supply vs. frequency v out p ? p (v) v dd = 10 v v dd = 5 v v dd = 2.7 v av = 10 r l = 2k c l = 10 pf t a = 25 c thd = 5% 11 10 9 8 7 6 5 4 3 2 1 0 02468 supply voltage (v) figure 12. supply current vs. supply voltage supply current / ch (ma) 600 500 400 300 200 100 0 10 12 14 16 18 25 c 105 c ? 40 c 9 8 7 6 5 4 3 2 1 0 90 100 110 120 v dd = 2.5 v 9 8 7 6 5 4 3 2 1 0
TLV271 http://onsemi.com 7 frequency (hz) figure 13. psrr vs. frequency psrr (db) r l = 2 k , input = 200 mv pp , av = 1, v dd = 2.5 v to 10 v, t a = 25 c 0 100 1k 10k 100k 1 100 10k 100k 1k 1m 10m frequency (hz) figure 14. open loop gain and phase vs. frequency open loop gain (db) 140 phase 10 v gain 10 v temperature ( c) figure 15. gain bandwidth product vs. temperature frequency (mhz) 4.5 ? 40 10 v 5 v 2.7 v r l = 2k c l = 10 pf 0 supply voltage (v) figure 16. slew rate vs. supply voltage slew rate (v/ s) 4 0.5 1 1.5 2 2.5 3.5 3 2 1 0 sr+ @ 105 c 120 100 80 60 40 20 0 ? 20 ? 20 0 20 40 60 80 100 ? 10 ? 20 ? 30 ? 40 ? 50 ? 60 ? 70 ? 80 ? 90 ? 100 ? 110 phase 5 v phase 2.7 v gain 5 v gain 2.7 v 2.5 v 4 3.5 3 2.5 2 3 sr ? @ 105 c phase margin ( c) 180 135 90 45 0 sr+ @ 25 c sr ? @ 25 c sr+ @ ? 40 c sr ? @ ? 40 c 10
TLV271 http://onsemi.com 8 free air temperature ( c) figure 17. slew rate vs. temperature slew rate (v/ s) 4 ? 60 ? 40 ? 20 0 20 40 60 80 100 120 sr+ 2.7 v sr ? 2.7 v sr+ 5 v sr ? 5 v sr+ 10 v sr ? 10 v 3 2 1 1 10k 10 1k 100 10 1 100 1k 10k frequency (hz) figure 18. voltage noise vs. frequency voltage noise (nv hz ) v s = 2.5 v v in = gnd, av = 22 rti figure 19. 2.5 v inverting large signal pulse response 250 mv/div 500 ns/div v s = 1.25 v av = ? 1 r l = 2 k v s = +2.5 v av = +1 r l = 2 k 250 mv/div 500 ns/div figure 20. 2.5 v non ? inverting large signal pulse response figure 21. 2.5 v inverting small signal pulse response 25 mv/div 500 ns/div v s = 1.25 v av = ? 1 r l = 2 k 25 mv/div 500 ns/div figure 22. 2.5 v non ? inverting small signal pulse response v s = +2.5 v av = +1 r l = 2 k 100k
TLV271 http://onsemi.com 9 250 mv/div 500 ns/div figure 23. 3 v inverting large signal pulse response v s = 1.5 v av = ? 1 r l = 2 k 250 mv/div 500 ns/div figure 24. 3 v non ? inverting large signal pulse response v s = +3 v av = +1 r l = 2 k 25 mv/div 500 ns/div figure 25. 3 v inverting small signal pulse response v s = 1.5 v av = ? 1 r l = 2 k v s = +3 v av = +1 r l = 2 k 25 mv/div 500 ns/div figure 26. 3 v non ? inverting small signal pulse response 500 mv/div 500 ns/div figure 27. 6 v inverting large signal pulse response v s = 3 v av = ? 1 r l = 2 k 500 mv/div 500 ns/div figure 28. 6 v non ? inverting large signal pulse response v s = +6 v av = +1 r l = 2 k
TLV271 http://onsemi.com 10 25 mv/div 500 ns/div figure 29. 6 v inverting small signal pulse response v s = +6 v av = ? 1 r l = 2 k 500 ns/div figure 30. 6 v non ? inverting small signal pulse response 25 mv/div v s = +6 v av = +1 r l = 2 k
TLV271 http://onsemi.com 11 applications + ? r1 r2 v o v ref v in v oh v o v ol hysteresis v inl v inh v ref mc1403 TLV271 ? + r1 v dd v dd v o 2.5 v r2 50 k 10 k v ref 5.0 k r c r c + ? v o for: f o = 1.0 khz r = 16 k c = 0.01 f v dd TLV271 TLV271 figure 31. voltage reference figure 32. wien bridge oscillator figure 33. comparator with hysteresis v o 2.5 v(1 r1 r2 ) v ref 1 2 v dd f o 1 2 rc v in l r1 r1 r2 (v ol v ref) v ref v in h r1 r1 r2 (v oh v ref) v ref h r1 r1 r2 (v oh v ol ) for less than 10% error from operational amplifier, ((q o f o )/bw) < 0.1 where f o and bw are expressed in hz. if source impedance varies, filter may be preceded with voltage follower buffer to stabilize filter parameters. given: f o = center frequency a(f o ) = gain at center frequency choose value f o , c v in figure 34. multiple feedback bandpass filter ? + v dd r3 r1 r2 v ref c c v o co = 10 c c o TLV271 then : r3 q f o c r1 r3 2a(f o ) r2 r1 r3 4q 2 r1 r3
TLV271 http://onsemi.com 12 package dimensions tsop ? 5 case 483 ? 02 issue k notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. 4. dimensions a and b do not include mold flash, protrusions, or gate burrs. mold flash, protrusions, or gate burrs shall not exceed 0.15 per side. dimension a. 5. optional construction: an additional trimmed lead is allowed in this location. trimmed lead not to extend more than 0.2 from body. dim min max millimeters a 3.00 bsc b 1.50 bsc c 0.90 1.10 d 0.25 0.50 g 0.95 bsc h 0.01 0.10 j 0.10 0.26 k 0.20 0.60 m 0 10 s 2.50 3.00 123 54 s a g b d h c j 0.7 0.028 1.0 0.039 mm inches scale 10:1 0.95 0.037 2.4 0.094 1.9 0.074 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.20 5x c ab t 0.10 2x 2x t 0.20 note 5 c seating plane 0.05 k m detail z detail z top view side view a b end view on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. TLV271/d publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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